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Designing
8-bits
carry Look Ahead Circuit
Engr. Ghalib Alhashmi
Table of Contacts
Chapter1: Introduction to Carry Look Ahead Adder/Subtractor
(CLA)…………………….…1
Chapter2: Design 8-bits CLA (Adder/Subtracror)………………………………………….…2
2.1 Defining
Problem…………………………………………………………….……3
2.1.1 The 8-bits Binary Addition
and Subtraction……………………………………………………...…....………3
2.2 Design 8-bits
CLA……….…………………...…………………………………..4
2.2.1 Truth Table……………….…………………………………………….4
2.2.2
K-map………....……………………………………………………….4
2.2.3 Design Using LogicWork
software………....……………………………………5
Chapter3: CLA Simulation……...……………………………………………………………..6
3.1 Addition …………………....…………………………………………………….6
3.2
Subtraction………………………………………………………………………..7
Conclusion…………..………………………………………………………………………...9
References……..……………………………………………………………………………..10
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Chapter1: Introduction to Carry Look Ahead
Adder/Subtractor CLA
The addition
and subtraction both are arithmetic operations that are performed in the
central processing unit (CPU). The arithmetic logical unit is a major part of
performing them. There are various circuits that can perform those operations.
The circuits are Carry look ahead (CLA), Binary parallel, BCD and other
circuits.
Let Ai
and Bi be addend, respectively, the outputs Si and Ci
denote sum and while Ci denotes carry into the position i.
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n-1
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i
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2
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1
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0
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Cn-1
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Ci
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C2
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C1
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C0
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An-1
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Ai
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A2
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A1
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A0
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Bn-1
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Bi
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B2
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B1
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B0
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Sn
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Sn-1
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Si
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S2
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S1
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S0
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Last carry out
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Figure 1.1 Simple circuit diagram of full adder
As shown in the Fig.1, the two internal signals Pi and Gi are given
by:
Pi= Ai XOR Bi …………………….. (1.1)
Gi= A AND Bi …….……………….. (1.2)
The output sum and carry can be determinate as:
Si=Pi XOR Ci ………………………..(1.3)
Ci+1=Gi OR (Pi AND Ci) ……….. (1.4)
Where Pi is
called carry propagation that can be produced by XORing Ai and Bi. Where Gi is
called carry generate that can be produced from ANDing Ai and Bi. Both Pi and
Gi only depend on the input Ai and Bi.
The i-bits
carry look ahead (CLA) consists of 3 levels of logic:
Input: entering
the input value of Ai and Bi in binary form. It may also consists XOR gate
(with input Bi and C0) to change the operation (addition or subtarction).
First level: generate
Pi and Gi signals. It consists of XOR gates and AND gates. The output signals
from this level are P’s and G’s.
Second level:
generate Ci signals as defined in expression (1.4). The output signals Ci come from
ORing Gi and the outcome from ANDing Ci-1 and Pi. This level consists of OR and
AND gates.
Third level:
generate the sum signals Si. XOR gates are valid in this level.
Output: shown
the output value in binary form.
Table 1.1:
Number of gate in each level on CLA for i-bits input.
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Gate
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LEVEL 1
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LEVEL 2
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LEVEL 3
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TOTAL
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AND
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i
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i
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0
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2i
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OR
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0
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i
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0
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i
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XOR
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i
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0
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I
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2i
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Table1.1 shows numbers
of gates that are required to design CLA. From expressions (1),(2),(3) and (4),
the number of AND gates is i ,if the input has i bits, in LEVEL1 also, LEVEL2
consists of i number of AND gates but LEVEL3 does not required any AND gate.
The OR gate appear only in LEVEL2 with number of i. The XOR gates are required
in LEVEL1 with i number of gate as well the same number on LEVEL3.
In this
project, the CLA will be considered to design and implement addition and
subtraction operations using LogicWork* software. The project will not
implemented hardwarely.
Chapter2: Design 8-bits CLA (Adder/Subtracror)
Design is an
important part, this chapter going through project design details. Designing
8-bits CLA consists of two parts. First part is defining problem clearly and then
design and simulate using LogicWork.
2.1 Defining Problem
Addition and subtraction are
operations that are needed to design in this project. The carry look ahead
principle is applied to them. The problem says: there are two inputs values for
each value of them has 8 bites.
2.1.1 The 8-bits Binary Addition and Subtraction
Let ( A=A7A6A5A4A3A2A1A0)
and (B=B7B6B5B4B3B2B1B0)
values each one of 8 bits are added. And let the result from this operation
(S=S7S6S5S4S3S2S1S0)
and let the carry that may be produced (C=C8C7C6C5C4C3C2C1).
The C0 has two majors. It works as an input and mode (change the
operations between addition and subtraction).
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n-1
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i
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2
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1
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0
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Cn-1
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Ci
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C2
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C1
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C0
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An-1
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Ai
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A2
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A1
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A0
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Bn-1
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Bi
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B2
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B1
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B0
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Sn
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Sn-1
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Si
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S2
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S1
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S0
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The maximum value of 8-bits is 28=256 when all the
8-bits filled by 1. When the 8-bits are 0’s, the value is the minimum.
(00000000)2 = (0)10 min-value
(11111111)2 =
(256)10 max-value
The result of any value of A that is added to min-value equals to
A. in this case, S=A and C=0. Example2.1:
add & subtract
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Subtract:
A=11001100
B=10101010
S=00100010
S9=0
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Add:
A=11001100
B=10101010
S=01110110
S9=1
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Let A=1100110011, B=10101010
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C=10001000
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C0=0
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C0=1
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C=10001000
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2.2
Truth table, Karnaugh map (K-map), Boolean expression and design
are considered on this section.
2.2.1 Truth Table
The truth table is a way to find Boolean expression. Table 2.2.1
is used to determinate for both asthmatic operations addition/subtraction.
Table 2.2.1
Truth table for designing CLA
|
i
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Ci Ai Bi
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Ci+1Si
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0
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à000
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00
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1
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001
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00
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2
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010
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01
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3
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011
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10
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4
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à100
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01
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5
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101
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10
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6
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110
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10
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7
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111
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11
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2.2.2 K-map
The K-map helps to get Boolean expression.
Table 2.2.2 K-map to get expression of Carry
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Ci\AiBi
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00
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01
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10
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11
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0
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0
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0
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0
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1
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0
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1
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From Table 2.2.2, the carry can be expressed as:
Ci+1=AiBi+Ci(AiÅBi)…………(2.2.1)
Note: the current carry depends to pervious carry and the inputs
values.
Table 2.2.3 K-map to get expression of sum
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Ci\AiBi
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00
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01
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10
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11
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0
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0
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0
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1
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0
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0
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From Table 2.2.3, the sum can be expressed as:
Si=Ci Å Ai Å Bi …………(2.2.2)
Let:
AiÅBi=
Pi ……………....(2.2.3)
And,
AiBi= Gi …………………..(2.2.4)
From expressions (2.2.3) and (2.2.3), the expressions (2.2.1)
and (2.2.2) can be modified as:
Ci+1=Gi+CiPi ……………(2.2.5)
Si=Ci Å
Pi ……………….(2.2.6)
2.2.3 Design Using LogicWork software
Figure 2.2.1 The final
design of CLA using LogicWork software
Chapter3: CLA Simulation
The Figure 2.2.1 shows CLA which
was completely tested and it worked functionally. In this chapter, the design
will be tested and simulated for different type of values. Screen shots will be
taken in each test.
3.1 Addition
Two testes are tried.
Note: at those testes the M=0.
3.1.1
ADD: 54 with 30
(54)10+ (30)10=(84)10=(00110110)2+(00011110)2
=(01010100)2
Figure 3.1.1 ADD:54,30 using CLA circuit (TEST3.1.1)
3.1.2
ADD: 254 with 256
(254)10+ (255)10=(509)10=(111111110)2+(11111111)2
=(11111101)2 with carry out
Figure 3.1.2 ADD: 254 with 256 (TEST3.1.2)
3.2 Subtraction
Two testes are tried.
Note: at those testes the M=1.
3.2.2
SUB:54, 30
(54)10- (30)10=(24)10=(00110110)2-(00011110)2
=(00001000)2
Figure 3.2.1 SUB: 54, 30(TEST3.2.1)
3.2.2
SUB:254, 255
(254)10 -(255)10=(-1)10=(111111110)2-(11111111)2
=(11111111)2’s=(00000001)2
Figure3.2.2: SUB:254,255(TEST3.2.2)
Conclusion:
Solving problem, Designing, test and simulation have been
conducted. The design of CLA is successfully worked and checked by Dr. Tariq
Jamel.
This project helps me to understand one of the most important topics
in course of Computer Organization and Architecture (ECCE5232. Moreover, good
skills: search knowledge from books and World wild Web, solving problem,
designing and testing errors can be added to me as an engineer.
If fact, the design requires 16 AND gates, 8 OR gates and 16 XOR
gates. It is unlike the expansion technique (method that depends only on carry
C0, Gi and Pi) which more gates. The expansion
technique is fast but expansive comparing to other which is slower but cheap.
The economic issue and fast machine are important factors that must be
considered in any design. The design in this project is considered to be cheap
and the fastness is not important in small circuit.
The improvements of the design are used expansion technique which
is more reliable for a big circuit. Also, using IC’s chips (which consists more
gates in one chip) is better than using single gate that did not found in the
regular market.
References
[1] William Stallinge, Computer
Organization and Architecture, sixth edition
[2]Handout of course ECCE5232, 2011, by Dr.Tariq Jamel, SQU
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