20120226

Designing 8-bits Carry Look Ahead Circuit


The aim of this project is to Obtain logic diagram for a complete 8-bit binary adder/subtractor circuit based on carry look-ahead principle and to simulate the circuit in LogicWorks. They are not allowed us to use any of the carry look-ahead ICs/decoder/multiplexer available in LogicWorks library but to design the entire circuit lonely using gates only. It also include timing diagrams to prove that the designed circuit does addition/subtraction correctly for various input combinations.




 The design of CLA is successfully worked and checked by Dr. TariqJamel. 
 ========================================================

Designing
8-bits carry Look Ahead Circuit

                                                                                             
         Engr. Ghalib  Alhashmi    

      =======================================================

Table of Contacts


Chapter1: Introduction to Carry Look Ahead Adder/Subtractor (CLA)…………………….…1
Chapter2: Design 8-bits CLA (Adder/Subtracror)………………………………………….…2
2.1 Defining Problem…………………………………………………………….……3
2.1.1 The 8-bits Binary Addition and Subtraction……………………………………………………...…....………3
2.2 Design 8-bits CLA……….…………………...…………………………………..4
2.2.1 Truth Table……………….…………………………………………….4
2.2.2 K-map………....……………………………………………………….4
2.2.3 Design Using LogicWork software………....……………………………………5
Chapter3: CLA Simulation……...……………………………………………………………..6
3.1 Addition …………………....…………………………………………………….6
3.2 Subtraction………………………………………………………………………..7
Conclusion…………..………………………………………………………………………...9
References……..……………………………………………………………………………..10





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Chapter1: Introduction to Carry Look Ahead Adder/Subtractor CLA


The addition and subtraction both are arithmetic operations that are performed in the central processing unit (CPU). The arithmetic logical unit is a major part of performing them. There are various circuits that can perform those operations. The circuits are Carry look ahead (CLA), Binary parallel, BCD and other circuits.
Let Ai and Bi be addend, respectively, the outputs Si and Ci denote sum and while Ci denotes carry into the position i.
Col#
n-1
i
2
1
0
carry
Cn-1
Ci
C2
C1
C0

An-1
Ai
A2
A1
A0

Bn-1
Bi
B2
B1
B0





Sn
Sn-1
Si
S2
S1
S0
Last carry out









Figure 1.1 Simple circuit diagram of full adder


As shown in the Fig.1, the two internal signals Pi and Gi are given by:
Pi= Ai XOR Bi   …………………….. (1.1)
Gi= A AND Bi …….……………….. (1.2)
The output sum and carry can be determinate as:
Si=Pi  XOR Ci ………………………..(1.3)
Ci+1=Gi OR (Pi AND Ci) ……….. (1.4)
Where Pi is called carry propagation that can be produced by XORing Ai and Bi. Where Gi is called carry generate that can be produced from ANDing Ai and Bi. Both Pi and Gi only depend on the input Ai and Bi.
The i-bits carry look ahead (CLA) consists of 3 levels of logic:
Input: entering the input value of Ai and Bi in binary form. It may also consists XOR gate (with input Bi and C0) to change the operation (addition or subtarction).
First level: generate Pi and Gi signals. It consists of XOR gates and AND gates. The output signals from this level are P’s and G’s.
Second level: generate Ci signals as defined in expression (1.4). The output signals Ci come from ORing Gi and the outcome from ANDing Ci-1 and Pi. This level consists of OR and AND gates.
Third level: generate the sum signals Si. XOR gates are valid in this level.
Output: shown the output value in binary form.
Table 1.1: Number of gate in each level on CLA for i-bits input.
Gate
LEVEL 1
LEVEL 2
LEVEL 3
TOTAL
AND
i
i
0
2i
OR
0
i
0
i
XOR
i
0
I
2i

Table1.1 shows numbers of gates that are required to design CLA. From expressions (1),(2),(3) and (4), the number of AND gates is i ,if the input has i bits, in LEVEL1 also, LEVEL2 consists of i number of AND gates but LEVEL3 does not required any AND gate. The OR gate appear only in LEVEL2 with number of i. The XOR gates are required in LEVEL1 with i number of gate as well the same number on LEVEL3.
In this project, the CLA will be considered to design and implement addition and subtraction operations using LogicWork* software. The project will not implemented hardwarely.

Chapter2: Design 8-bits CLA (Adder/Subtracror)


Design is an important part, this chapter going through project design details. Designing 8-bits CLA consists of two parts. First part is defining problem clearly and then design and simulate using LogicWork.

 

2.1 Defining Problem


 Addition and subtraction are operations that are needed to design in this project. The carry look ahead principle is applied to them. The problem says: there are two inputs values for each value of them has 8 bites. 

2.1.1 The 8-bits Binary Addition and Subtraction

Let ( A=A7A6A5A4A3A2A1A0) and (B=B7B6B5B4B3B2B1B0) values each one of 8 bits are added. And let the result from this operation (S=S7S6S5S4S3S2S1S0) and let the carry that may be produced (C=C8C7C6C5C4C3C2C1). The C0 has two majors. It works as an input and mode (change the operations between addition and subtraction).
Col#
n-1
i
2
1
0
carry
Cn-1
Ci
C2
C1
C0

An-1
Ai
A2
A1
A0

Bn-1
Bi
B2
B1
B0





Sn
Sn-1
Si
S2
S1
S0

The maximum value of 8-bits is 28=256 when all the 8-bits filled by 1. When the 8-bits are 0’s, the value is the minimum.
(00000000)2 = (0)10 min-value
 (11111111)2 = (256)10 max-value
The result of any value of A that is added to min-value equals to A. in this case, S=A and C=0. Example2.1: add & subtract
Subtract:
A=11001100
B=10101010
S=00100010
S9=0
Add:
A=11001100
B=10101010
S=01110110
S9=1

Let       A=1100110011, B=10101010

C=10001000
C0=0
C0=1
C=10001000

 








2.2 Design 8-bits CLA

Truth table, Karnaugh map (K-map), Boolean expression and design are considered on this section.

2.2.1 Truth Table

The truth table is a way to find Boolean expression. Table 2.2.1 is used to determinate for both asthmatic operations addition/subtraction.
Table 2.2.1 Truth table for designing CLA
i
Ci Ai Bi
Ci+1Si
0
à000
00
1
     001
00
2
     010
01
3
     011
10
4
à100
01
5
     101
10
6
     110
10
7
     111
11

2.2.2 K-map

The K-map helps to get Boolean expression.
Table 2.2.2 K-map to get expression of Carry
Ci\AiBi
00
01
10
11
0
0
0
1
0
1
0
1
1
1

From Table 2.2.2, the carry can be expressed as:
Ci+1=AiBi+Ci(AiÅBi)…………(2.2.1)
Note: the current carry depends to pervious carry and the inputs values.
Table 2.2.3 K-map to get expression of sum
Ci\AiBi
00
01
10
11
0
0
1
0
1
1
1
0
1
0

From Table 2.2.3, the sum can be expressed as:
Si=Ci Å Ai Å Bi …………(2.2.2)

Let:
AiÅBi= Pi  ……………....(2.2.3)
And,
AiBi= Gi …………………..(2.2.4)
From expressions (2.2.3) and (2.2.3), the expressions (2.2.1) and (2.2.2) can be modified as:
Ci+1=Gi+CiPi ……………(2.2.5)
Si=Ci Å Pi ……………….(2.2.6)

2.2.3 Design Using LogicWork software


Figure 2.2.1 The final design of CLA using LogicWork software




Chapter3: CLA Simulation


The Figure 2.2.1 shows CLA which was completely tested and it worked functionally. In this chapter, the design will be tested and simulated for different type of values. Screen shots will be taken in each test.

3.1 Addition

Two testes are tried.
Note: at those testes the M=0.

3.1.1TEST 

ADD: 54 with 30
(54)10+ (30)10=(84)10=(00110110)2+(00011110)2 =(01010100)2




Figure 3.1.1 ADD:54,30 using CLA circuit (TEST3.1.1)


 3.1.2TEST 

ADD: 254 with 256
(254)10+ (255)10=(509)10=(111111110)2+(11111111)2 =(11111101)2 with carry out


Figure 3.1.2 ADD: 254 with 256 (TEST3.1.2)

 

 

3.2 Subtraction

Two testes are tried.
Note: at those testes the M=1.

3.2.2TEST 

SUB:54, 30
(54)10- (30)10=(24)10=(00110110)2-(00011110)2 =(00001000)2
Figure 3.2.1 SUB: 54, 30(TEST3.2.1)


3.2.2TEST 

SUB:254, 255
 (254)10 -(255)10=(-1)10=(111111110)2-(11111111)2 =(11111111)2’s=(00000001)2

    Figure3.2.2: SUB:254,255(TEST3.2.2)

Conclusion:

Solving problem, Designing, test and simulation have been conducted. The design of CLA is successfully worked and checked by Dr. Tariq Jamel.
This project helps me to understand one of the most important topics in course of Computer Organization and Architecture (ECCE5232. Moreover, good skills: search knowledge from books and World wild Web, solving problem, designing and testing errors can be added to me as an engineer.
If fact, the design requires 16 AND gates, 8 OR gates and 16 XOR gates. It is unlike the expansion technique (method that depends only on carry C0, Gi and Pi) which more gates. The expansion technique is fast but expansive comparing to other which is slower but cheap. The economic issue and fast machine are important factors that must be considered in any design. The design in this project is considered to be cheap and the fastness is not important in small circuit.
The improvements of the design are used expansion technique which is more reliable for a big circuit. Also, using IC’s chips (which consists more gates in one chip) is better than using single gate that did not found in the regular market.















References


[1] William Stallinge, Computer   Organization and Architecture, sixth edition
[2]Handout of course ECCE5232, 2011, by Dr.Tariq Jamel, SQU






































 




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